Leakage Control Techniques in Nanometer CMOS

Among the different leakage currents in the nanometer CMS, the subthreshold and gate leakage are the most dominant. While the latter is mainly due to electron tunnelling from the gate to the substrate, the former is caused by many other factors. As a result, the leakage control techniques to be discussed will focus more on subthreshold currents. Over the years, many techniques have been developed to reduce the subthreshold currents in both the active and standby modes in order to minimize the total power consumption of CMOS circuits.

While the standby leakage currents are wasted currents when the circuit is in idle mode where no computation takes place, the active leakage currents are wasted current when the circuit is in use. Generally, reduction of leakage currents involves application of different device and circuit level techniques. At the device level, it involves controlling the doping profiles and physical dimensions of transistors while at the circuit level, it involves the manipulation of threshold voltage (Vth) and source biasing of the transistor. learning boards

A. Circuit Level Leakage Control Techniques

i) Multi Vth Techniques
This technique involves fabrication of two types of transistors, high Vth and low Vth transistors, on a chip. The high Vth is used to lower the subthreshold leakage current, while the low Vth is used to enhance performance through faster operation. Obtaining these different types of transistors is done through controlled channel doping, different oxide thickness, multiple channel lengths or multiple body biases. Notwithstanding, with technology scaling and continuous decrease in the supply voltage, the implementation of the high Vth transistor will become a major practical challenge.

Dual threshold method
In logic circuits, leakage current can be reduced by assigning higher Vth to devices in non-critical paths, while maintaining performance with low Vth in the critical paths. This technique is applicable to both standby and active mode leakage power dissipation control. It ensures that the circuit operates at a high speed and reduced power dissipation.

Multi-Threshold Voltage Method
This method uses a high Vth device to gate supply voltage from a low Vth logic block thereby creating a virtual power rail instead of directly connecting the block to the main power rail. The high Vth switches are used to disconnect the power supplies during the standby state, resulting in very low leakage currents set by the high Vth of the series logic block. In active mode operation, the high Vth transistors are switched on and the logic block, designed with low Vth, operates at fast speed.

This enables leakage current reduction via the high Vth and enhanced performance via the low Vth block. Alternatively, this system could be implemented with a high Vth NMOS transistor connected between the GND and the low Vth block. The NMOS transistor insertion is preferred to the PMOS since it has a lower ON-resistance at the same width and consequently can be sized smaller. The use of these transistors increases circuit delay and area. Besides, to retain data during standby mode, extra high Vth memory circuit is needed.


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